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Please use the Registration page to register for the workshops. All workshops will send emails to registered participants.

Open-Source Source-to-Source Transformation for High-Level Synthesis

27th February 2022, 1:30pm–5pm PST

Organizer: Jason Cong (UCLA)

Workshop Link

As high-level synthesis (HLS) tools are getting more and more mature, HLS synthesizable C/C++/OpenCL are becoming popular as new design entry languages for FPGA accelerator implementation. However, the pragmas and coding style associated with the HLS input program have significant impact to the final accelerator design quality. Therefore, there are growing interests in developing source-to-source transformation and optimization tools to automatically generate HLS-friendly C/C++/OpenCL code. The recent community-wide effort on MLIR (multi-level intermediate representation) and open-source of the Merlin Compiler by Xilinx (via acquisition of Falcon Computing Solutions) open more opportunities for source-to-source transformation and optimization. This workshop has six exciting talks about the latest progress in this area. It ends with a panel of leaders from academia and industry on FPGA synthesis to discuss “What’s next on source-to-source transformation?”

Introduction to Vitis AI development Tools Flow

27th February 2022, 8am–noon PST

Organizer: Parimal Patel (Xilinx)

Max Participants: 50

In this tutorial we will describe Xilinx machine learning solutions with the Vitis AI development tools. We will list and explain the supported frameworks, network modes, and pre-trained models for cloud and edge applications. The Vitis AI development environment features, the tool flow, the software stack, and supported deployment platforms will be explained. Various DPU configurations to optimize a model for an edge application will be covered. High-level libraries and the APIs of the Xilinx AI Library will be identified. You will go through the tool flow using Caffe, TensorFlow, and PyTorch frameworks. The labs will demonstrate the important steps involved in developing applications using these frameworks. The labs will be done using AWS instances, but the gained knowledge applies to other Vitis AI platforms based on on Alveo, Versal and MPSoC boards. You will also do a lab that guides you through the steps involved in creating a complete edge targeting application.

Nios V: RISC-V Based Processors for Intel® FPGAs

27th February 2022, 9am–9:30am PST

Organizer: Shreya Mehrotra (Intel)

Nios® V soft processors are based on the open-source RISC-V instruction set architecture. In this session, we will provide an overview of the first of the Nios V processor series, the Nios V/m processor. We will also talk about the hardware and software development flows on Nios V using the traditional FPGA development tools like Quartus and Platform Designer that users are familiar with. Finally, you’ll learn about the growing and diverse Nios V ecosystem that gives you access to your favorite IDEs, compilers, debuggers, and operating systems.

Hands-On Tutorial: Introduction to oneAPI with Intel® FPGAs

27th February 2022, 10am–noon PST

Organizer: Ogheneuriri Oderhohwo (Intel)

DPC++ is a programming language based on SYCL that can be used to target algorithms to an FPGA or other devices in a heterogeneous compute environment with an x86 host. This tutorial will teach you how to use the oneAPI software model to create Data Parallel C++ programs to target supported FPGA acceleration cards. You will learn how your source code is interpreted by the compiler to build a custom hardware datapath. You will learn the 3-step flow for development: (1) emulation, (2) using the static optimization report to fine tune your implementation, and (3) compiling a bitstream for the FPGA. You will be able to practice the various steps in development using JupyterLab on the Intel DevCloud for oneAPI.