Workshop and Tutorial Schedule

All times shown in Pacific Standard Time (UTC−8)

To sign up for workshops and tutorials, please use the registration link on the conference registration page (https://www.isfpga.org/registration/). Some events may require additional registration, see each event for details.

Lunch will not be provided, but we will have a lunch break from 12:00PM to 1:30PM

Date Time Name
February 22 08:00AM - 12:00PM 2nd Workshop on Domain-Specialized FPGAs
February 22 08:00AM - 12:00PM CEDR: A Holistic Software and Hardware Design Environment for Hardware Agnostic Application Development and Deployment on FPGA-Integrated Heterogeneous Systems
February 22 10:30AM - 11:00AM Break AM
February 22 12:00PM - 01:30PM Lunch (not provided by the conference)
February 22 01:30PM - 05:30PM SODA Synthesizer: Accelerating Artificial Intelligence Applications with an End-to-End Compiler-Based Toolchain
February 22 01:30PM - 05:30PM REMU: An FPGA-based Open-source Replayable EMUlator for System-level Evaluating and Debugging Processors
February 22 01:30PM - 05:30PM Building an AI Video Pipeline for Real-Time Classification on Altera Agilex 5
February 22 03:00PM - 03:30PM Break PM

Workshop and Tutorial Details

2nd Workshop on Domain-Specialized FPGAs

As FPGA architectures rapidly evolve beyond general-purpose fabrics, the industry and research community is moving toward domain-specialized FPGAs – from ML-centric fabrics to packet processing FPGAs, RFSoCs, emulation-oriented FPGAs, and more. 

Building on the success of last year’s inaugural event, the 2nd Workshop on Domain-Specialized FPGAs (co-located with ISFPGA 2026) will bring together researchers and practitioners from across domains to advance the state of domain-specialized FPGA architectures, benchmarks, and CAD. This workshop will provide a forum for sharing benchmarks, sparking creative discussions, and surfacing visionary directions in FPGA specialization.

This year we will have a set of presentations on benchmarks from various application domains, and on bold ideas/positions about FPGA architecture and CAD from the community. The workshop will also include a panel discussion where experts from the academia and industry will discuss the future of domain-specialized FPGAs. The panel will be moderated and will include audience questions.Please see https://sites.google.com/view/domain-specialized-fpgas-2026/ for more information.

Organizers: Aman Arora (Arizona State University), Abhishek Kumar Jain (AMD), Andrew Schmidt (AMD)

CEDR: A Holistic Software and Hardware Design Environment for Hardware Agnostic Application Development and Deployment on FPGA-Integrated Heterogeneous Systems

As FPGAs are being embedded in all layers of computing infrastructure from edge to HPC scale, system designers continue to explore design methodologies that leverage increased levels of heterogeneity to push performance within the target performance goals or constraints. In line with this objective, we have developed CEDR, an open-source, unified compilation and runtime framework designed for FPGA-integrated heterogeneous systems, initially created as part of the DARPA DSSoC program. Our framework empowers users to seamlessly develop, compile, and deploy applications on off-the-shelf heterogeneous computing platforms. The framework is portable across a wide range of Linux-based systems, enabling seamless migration between platforms. Building on the previous CEDR tutorials conducted at ESWEEK’23, ISFPGA’24, ISFPGA’25, ESWEEK’25, and PACT’25, this tutorial caters to audiences with diverse backgrounds and varying levels of expertise through hands-on activities tailored to three user types: application developers, system designers, and resource management heuristic developers. For the 2026 edition, we partner with AMD to provide learning experience through hands-on exercises using AMD Xilinx FPGA-based SoCs and discussions around emerging challenges in heterogeneous computing.

CEDR is currently being leveraged in basic research and its utility has been validated through a diverse set of real-world applications by General Dynamics, Collins Aerospace, and the Johns Hopkins University Applied Physics Laboratory, alongside several academic collaborators. Additionally, it has undergone independent evaluation by the Carnegie Mellon University Software Engineering Institute. With its easy-to-use Application Programming Interface (API)-based programming model, CEDR has extended support and compatibility across programming models (GNURadio, PyTorch, Taskflow) and architectures (RISC-V, GPU, FPGA, and ARM-based SoCs), making it a highly versatile runtime for heterogeneous computing. In recent tutorials at ISFPGA’25, ESWEEK’25, and PACT’25, participants gained hands-on experience with CEDR on implementing applications and analyzing performance across diverse workload scenarios and scheduling heuristics using FPGA-based heterogeneous SoCs. Through our partnership with AMD, attendees in ESWEEK’25 and PACT’25 executed their implementations directly on AMD’s AUP-ZU3 FPGA boards. To enable repeatability and independent learning, all tutorial materials, including step-by-step instructions, test applications, and reference FPGA images, are publicly available.

Please see https://ua-rcl.github.io/projects/cedr/tutorials/isfpga26.html for more information.

Organizers: Serhan Gener (University of Arizona), Sahil Hassan (University of Arizona), Ali Akoglu (University of Arizona)

SODA Synthesizer: Accelerating Artificial Intelligence Applications with an End-to-End Compiler-Based Toolchain

The explosive growth of new algorithms in data analysis and artificial intelligence demands efficient domain-specific FPGA accelerators that can be designed and deployed quickly. Unfortunately, designing custom FPGA hardware requires expertise in hardware design, hardware description languages (HDLs), and FPGA-specific optimization techniques. New approaches that overcome the design expertise gap while leveraging FPGA-specific features and keeping pace with algorithm evolution are essential for enabling agile reconfigurable computing design flows. High-Level Synthesis (HLS) promises to bridge this gap for FPGA design. While successful, conventional HLS methods have primarily focused on accelerating loop-based kernels from C/C++ specifications with custom pragmas. These approaches work well for regular, compute-intensive applications but struggle with irregular, data-intensive workloads common in modern AI applications, such as graph analytics and sparse neural networks. Recently, new methodologies have emerged to support parallel programming models and interface with higher-level frameworks typically adopted by domain scientists. The emergence of higher-level compilation infrastructures, such as the Multi-Level Intermediate Representation (MLIR) framework, has created new opportunities to develop methodologies for co-designing more efficient FPGA accelerators and exploring reconfigurable system architectures.

In this tutorial, we aim to provide an overview of state-of-the-art methodologies, opportunities, perspectives, and persistent challenges for broad adoption of HLS-based approaches to enable co-design of complex domain-specific FPGA accelerators for artificial intelligence. We will emphasize what distinguishes modern compiler-based approaches from conventional HLS tools, including:

  • Task-parallel synthesis methodologies: Support for multi-threaded accelerators that can handle irregular, data-driven parallelism beyond traditional loop pipelining
  • Coarse-grained dataflow architectures: Automated generation of dataflow designs that exploit producer-consumer parallelism across multiple functional units
  • System-level optimization: Hardware/software co-design and partitioning from high-level framework specifications
  • Cross-platform portability: Unified flow supporting multiple FPGA vendors (Xilinx/AMD, Intel/Altera) and ASIC targets, enabling design space exploration across implementation technologies

After this high-level overview, we will provide hands-on demonstration of integration between a state-of-the-art open-source HLS tool (Bambu, from Politecnico di Milano’s Panda framework: https://panda.dei.polimi.it ) with a high-level front-end and optimizer for domain-specific frameworks (SODA-OPT, developed using MLIR: https://github.com/pnnl/soda-opt ). SODA-OPT performs hardware/software partitioning from specifications derived from high-level data science and machine learning Python frameworks, applying domain-specific optimizations to enhance the HLS process. The entire toolchain connects with both commercial and open-source EDA tools, providing flexibility from Python specifications to FPGA bitstreams or ASIC layouts, enabling true exploration of the hardware design space.

Please see https://hpc.pnl.gov/SODA/page1.html for more information.

Organizers: Vito Giovanni Castellana (Pacific Northwest National Laboratory), Fabrizio Ferrandi (Politecnico di Milano), Antonino Tumeo (Pacific Northwest National Laboratory)


REMU: An FPGA-based Open-source Replayable EMUlator for System-level Evaluating and Debugging Processors

Abstract—Over the past decade, Shift-left integration and evaluation of hardware (HW) and software (SW) design have been increasingly crucial in the pre-silicon validation procedure when developing processor-centric computing systems. FPGA emulation offers essential cycle-accuracy for performance evaluation. However, limited HW-SW visibility in current open-source frameworks hinders effective system-level inspection and debugging.

In this half-day tutorial, we present REMU, an open-source academic FPGA-based emulation framework. REMU enables cost-effective hardware checkpointing and deterministic replay to acquire fully bit-accurate and cycle-accurate visibility of target processors as well as system components (i.e., memory and peripherals), It supports integration of real PCIe devices to implement system-level modeling and evaluation. Specifically, we will first introduce REMU’s fundamental techniques and workflow to build a brief but comprehensive picture of REMU for the audience. Then, the attendees will experience REMU from the system-level perspective with practical examples aiming for cycle-accurate performance evaluation and bit-accurate HW-SW co-debugging using our custom FPGA cloud services. Finally, we will discuss our plans for REMU and introduce HeteroProto, our latest automated framework designed to scale validation from single-FPGA debugging to heterogeneous multi-FPGA prototyping. This tutorial showcases a practical cloud-based FPGA application scenario, driven by our custom automated EDA flow for instrumentation and deployment.
Please see https://remu-toolkit.github.io/ for more information.

Organizers: Ke Zhang (Institute of Computing Technology, Chinese Academy of Sciences), Guanghui Hu (ShanghaiTech University), Panyu Wang (University of Chinese Academy of Sciences), Congrong Ye (Institute of Computing Technology, Chinese Academy of Sciences), Congwu Zhang (Institute of Computing Technology, Chinese Academy of Sciences), Yazhou Wang (Institute of Computing Technology, Chinese Academy of Sciences), Si Zhang (Institute of Computing Technology, Chinese Academy of Sciences), Shiqi Liu (Institute of Computing Technology, Chinese Academy of Sciences), Bibo Yang (Institute of Computing Technology, Chinese Academy of Sciences), Mingyu Chen (Institute of Computing Technology, Chinese Academy of Sciences)

Building an AI Video Pipeline for Real-Time Classification on Altera Agilex 5

This hands-on workshop guides participants through the full process of building a modern video and AI system on FPGA hardware. It begins with practical instruction in Visual Designer Studio, where attendees learn to create modular video pipelines, work with key ISP components, and configure high-performance interfaces such as AXI4‑Stream and Avalon‑MM. The session also covers essential system considerations like clocking, reset strategies, and hardware validation through LabsLand.

The workshop then moves into AI integration. Participants explore edge AI use cases, train a compact convolutional neural network for classification, and generate custom accelerator IP for Agilex 5 devices. By the end, attendees will have completed an end-to-end workflow that takes raw video input through real-time AI inference using Quartus Pro, Visual Designer Studio, and FPGA AI Suite.

This tutorial is designed for anyone who wants practical experience in unifying video processing and AI acceleration within an FPGA workflow suitable for edge computing application 

Topics include:

  • Hierarchical system design and subsystem composition
  • Modular accelerator construction using standard FPGA interfaces
    • AXI4-Stream (dataflow)
    • Avalon-MM (control and configuration)
  • Clock-domain and reset-domain management
  • Address mapping and interconnect configuration
  • Static system validation and HDL generation
  • Full compilation to FPGA bitstream
  • Integration of FPGA AI Suite generated AI inference accelerators

Organizers: Cinthya Rosales (Altera), Rama Venkata (Altera)