Technical Program
All times shown in Pacific Standard Time (UTC-8)
Links will be emailed to registrants.
Breakfast is available daily in the kitchen. Menu may vary by locale.
Sunday, February 27, 2022
Workshops and Tutorials are listed separately. All workshops and tutorials are included in the conference fee, but may require separate registration in order to manage capacity. Check each event for additional registration requirements.
Monday, February 28, 2022
(Bold titles indicate best paper candidates)
Time (PST) | Topic |
Title | Authors |
---|---|---|---|
08:00 | Opening Session | Michael Adler, Paolo Ienne | |
08:15 | Architecture and CAD |
RapidStream: Parallel Physical Implementation of FPGA HLS Designs ![]() ![]() ![]() |
Licheng Guo |
, Pongstorn Maidee , Yun Zhou , Chris Lavin , Jie Wang , Yuze Chi , Weikang Qiao , Alireza Kaviani , Zhiru Zhang , and Jason Cong
How to Shrink My FPGAs - Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics | King Lok Chung | , Nguyen Dao , Jing Yu , and Dirk Koch||
Revisiting PathFinder Routing Algorithm | Yue Zha | and Jing "Jane" Li||
Multi-input Serial Adders for FPGA-like Computational Fabric (short) | Herman Schmit | and Matthew Denton||
Towards Agile DNN Accelerator Design Using Incremental Synthesis on FPGAs (short) | Qingcheng Xiao | and Yun Liang||
09:15 | Keynote |
Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene | Zsolt Tőkei |
10:15 | Break | ||
10:30 | Poster Session 1 | ||
11:15 | High-Level Tools and Abstractions |
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV ![]() ![]() |
Yixiao Du | , Yuwei Hu , Zhongchun Zhou , and Zhiru Zhang
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication ![]() ![]() ![]() |
Linghao Song | , Yuze Chi , Atefeh Sohrabizadeh , Young-kyu Choi , Jason Lau , and Jason Cong||
HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs ![]() ![]() ![]() |
Shaojie Xiang | , Yi-Hsiang Lai , Yuan Zhou , Hongzheng Chen , Niansong Zhang , Debjit Pal , and Zhiru Zhang||
Finding and Finessing Static Islands in Dynamically Scheduled Circuits | Jianyi Cheng | , John Wickerson , and George A. Constantinides||
12:15 | End of Day 1 |
Tuesday, March 1, 2022
(Bold titles indicate best paper candidates)
Time (PST) | Topic |
Title | Authors and Presenters |
---|---|---|---|
08:00 | Machine Learning |
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference ![]() ![]() ![]() |
Erwei Wang | , James J. Davis , Georgios-Ilias Stavrou , Peter Y. K. Cheung , George A. Constantinides , and Mohamed Abdelfattah
N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores | Yu Gong | , Zhihan Xu , Zhezhi He , Weifeng Zhang , Xiaobing Tu , Xiaoyao Liang , and Li Jiang||
HP-GNN: Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform | Yi Chien Lin | , Bingyi Zhang , and Viktor K. Prasanna||
FILM-QNN: Efficient FPGA Acceleration of Deep Neural Networks with Intra-Layer, Mixed-Precision Quantization | Mengshu Sun | , Zhengang Li , Alec Lu , Yanyu Li , Sung-En Chang , Xiaolong Ma , Xue Lin , and Zhenman Fang||
An FPGA-based RNN-T Inference Accelerator with PIM-HBM (short) | Shinhaeng Kang | , Sukhan Lee , Byeongho Kim , Hweesoo Kim , Kyomin Sohn , Nam Sung Kim , and Eojin Lee||
09:10 | Hall of Fame Papers |
||
09:20 | Keynote |
The Virtuous Cycles of Determinism: Programming Groq's Tensor Streaming Processor | Satnam Singh |
10:20 | Break | ||
10:30 | Poster Session 2 | ||
11:15 | Applications |
REMOT: A Hardware-Software Architecture for Attention-Guided Multi-Object Tracking with Dynamic Vision Sensors on FPGAs ![]() ![]() ![]() |
Yizhao Gao | , Song Wang , and Hayden Kwok-Hay So
Accelerating Constraint-Based Causal Discovery by Shifting Speed Bottleneck | Ce Guo | and Wayne Luk||
Co-Design for Energy Efficient and Fast Genomic Search: Interleaved Bloom Filter on FPGA | Marius Knaust | , Enrico Seiler , Knut Reinert , and Thomas Steinke||
Accelerating SSSP for Power-Law Graphs ![]() ![]() ![]() |
Yuze Chi | , Licheng Guo , and Jason Cong||
12:15 | Best Paper Award and Closing Session | Michael Adler, Paolo Ienne |
Poster Session 1 (February 28)
Session Chair: Lana Josipović
Title | Authors |
---|---|
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA | Mingqiang Huang | , Yucen Liu , Quan Cheng , Shuxin Yang , Kai Li , Junyi Luo , Zhengke Yang , Qiufeng Li , and Hao Yu
Automated Accelerator Optimization Aided by Graph Neural Networks | Atefeh Sohrabizadeh | , Yunsheng Bai , Yizhou Sun , and Jason Cong
Efficient FPGA-based ECDSA Verification Engine For Permissioned Blockchains | Rashmi Agrawal | , Ji Yang , and Haris Javaid
End-to-End Acceleration of Homomorphic Encrypted CNN Inference on FPGAs | Tian Ye | , Rajgopal Kannan , and Viktor K. Prasanna
FPGA Accelerators for Robust Visual SLAM on Humanoid Robots | Maria Rafaela Gkeka | , Alexandros Patras , Nikolaos Tavoularis , Stylianos Piperakis , Emmanouil Hourdakis , Panos Trahanias , Christos D. Antonopoulos , Spyros Lalis , and Nikolaos Bellas
Hardware Acceleration of Nonparametric Belief Propagation for Efficient Robot Manipulation | Yanqi Liu | , Theo Guerin , Anthony Opipari , and Ruth Iris Bahar
HMT: A Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for High-Performance Authentication | Rakin Muhammad Shadab | , Yu Zou , Sanjay Gandham , Amro Awad , and Mingjie Lin
MathRAMs: Configurable Fused Compute-Memory Blocks for FPGAs | Aman Arora | , Aatman Borda , Anand Tanmay , Bagus Hanindhito , and Lizy John
Synthesized Garbage Collection for FPGA Accelerators | Martha Barker | , Martha Kim , and Stephen A. Edwards
Poster Session 2 (March 1)
Session Chair: Stefan Nikolić
Title | Authors |
---|---|
DecGNN: A Framework for Mapping Decoupled GNN Models onto CPU-FPGA Heterogeneous Platform | Bingyi Zhang | , Hanqing Zeng , and Viktor K. Prasanna
FPGA-based Trainable Autoencoder for Communication Systems | Jonas Ney | , Sebastian Dörner , Matthias Herrmann , Mohammad Hassani Sadi , Jannis Clausius , Stephan ten Brink , and Norbert Wehn
Highly Scalable Runtime Countermeasure Against Microprobing Attacks on Die-to-Die Interconnections in System-in-Package | Zhenyu Xu | , Thomas Mauldin , Qing Yang , and Tao Wei
HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers | Yuanlong Xiao | and Andre DeHon
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA | Mohammad Bagherbeik | , Wentao Xu , Seyed Farzad Mousavi , Kouichi Kanda , Hirotaka Tamura , and Ali Sheikholeslami
An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGA | Yukui Luo | , Yuheng Zhang , Shijin Duan , and Xiaolin Xu
SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation | Atefeh Sohrabizadeh | , Yuze Chi , and Jason Cong
Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform | Jiafeng Xie | , Pengzhou He , and Tianyou Bao
Yosys+Odin-II: The Odin-II Partial Mapper with Yosys Coarse-grained Netlists in VTR | Seyed Alireza Damghani | and Kenneth B. Kent