Program

Technical Program

All times shown in Pacific Standard Time (UTC-8)
Links will be emailed to registrants.

Breakfast is available daily in the kitchen. Menu may vary by locale.

Sunday, February 27, 2022

Workshops and Tutorials are listed separately. All workshops and tutorials are included in the conference fee, but may require separate registration in order to manage capacity. Check the each event for additional registration requirements.

Monday, February 28, 2022

(Bold titles indicate best paper candidates)

Time (PST)	Topic	Title	Authors
08:00	Opening Session		Michael Adler, Paolo Ienne
08:15	Architecture and CAD	RapidStream: Parallel Physical Implementation of FPGA HLS Designs	Licheng Guo (UCLA), Pongstorn Maidee (Xilinx), Yun Zhou (Ghent University), Chris Lavin (Xilinx), Jie Wang (UCLA), Yuze Chi (UCLA), Weikang Qiao (UCLA), Alireza Kaviani (Xilinx), Zhiru Zhang (Cornell), and Jason Cong (UCLA)
		How to Shrink My FPGAs - Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics	King Lok Chung (University of Manchester), Nguyen Dao (University of Manchester), Jing Yu (University of Manchester), and Dirk Koch (University of Manchester)
		Revisiting PathFinder Routing Algorithm	Yue Zha (University of Pennsylvania) and Jing "Jane" Li (University of Pennsylvania)
		Multi-input Serial Adders for FPGA-like Computational Fabric (short)	Herman Schmit (Google) and Matthew Denton (Google)
		Towards Agile DNN Accelerator Design Using Incremental Synthesis on FPGAs (short)	Qingcheng Xiao (Peking University) and Yun Liang (Peking University)
09:15	Keynote	Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene	Zsolt Tőkei (imec)
10:15	Break
10:30	Poster Session 1
11:15	High-Level Tools and Abstractions	High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV	Yixiao Du (Cornell University), Yuwei Hu (Cornell University), Zhongchun Zhou (Cornell University), and Zhiru Zhang (Cornell University)
		Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication	Linghao Song (UCLA), Yuze Chi (UCLA), Atefeh Sohrabizadeh (UCLA), Young-kyu Choi (Inha University), Jason Lau (UCLA), and Jason Cong (UCLA)
		HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs	Shaojie Xiang (Cornell University), Yi-Hsiang Lai (Cornell University), Yuan Zhou (Cornell University), Hongzheng Chen (Cornell University), Niansong Zhang (Cornell University), Debjit Pal (Cornell University), and Zhiru Zhang (Cornell University)
		Finding and Finessing Static Islands in Dynamically Scheduled Circuits	Jianyi Cheng (Imperial College London), John Wickerson (Imperial College London), and George A. Constantinides (Imperial College London)
12:15	End of Day 1

Tuesday, March 1, 2022

(Bold titles indicate best paper candidates)

Time (PST)	Topic	Title	Authors
08:00	Machine Learning	Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference	Erwei Wang (Imperial College London), James J. Davis (Imperial College London), Georgios-Ilias Stavrou (Imperial College London), Peter Y. K. Cheung (Imperial College London), George A. Constantinides (Imperial College London), and Mohamed Abdelfattah (Cornell University)
		N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores	Yu Gong (Shanghai Qi Zhi Institute), Zhihan Xu (Shanghai Qi Zhi Institute), Zhezhi He (Shanghai Jiao Tong University), Weifeng Zhang (Alibaba Group US Inc.), Xiaobing Tu (Alibaba Group), Xiaoyao Liang (Shanghai Jiao Tong University), and Li Jiang (Shanghai Jiaotong University)
		HP-GNN: Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform	Yi Chien Lin (University of Southern California), Bingyi Zhang (University of Southern California), and Viktor K. Prasanna (University of Southern California)
		FILM-QNN: Efficient FPGA Acceleration of Deep Neural Networks with Intra-Layer, Mixed-Precision Quantization	Mengshu Sun (Northeastern University), Zhengang Li (Northeastern University), Alec Lu (Simon Fraser University), Yanyu Li (Northeastern University), Sung-En Chang (Northeastern University), Xiaolong Ma (Northeastern University), Xue Lin (Northeastern University), and Zhenman Fang (Simon Fraser University)
		An FPGA-based RNN-T Inference Accelerator with PIM-HBM (short)	Shinhaeng Kang (Samsung Electronics), Sukhan Lee (Samsung Electronics), Byeongho Kim (Seoul National University), Hweesoo Kim (Samsung Electronics), Kyomin Sohn (Samsung Electronics), Nam Sung Kim (Samsung Electronics), and Eojin Lee (Inha University)
09:10	Hall of Fame Papers (Maya Gokhale)
09:15	Keynote	The Virtuous Cycles of Determinism: Programming Groq's Tensor Streaming Processor	Satnam Singh (Groq)
10:15	Break
10:30	Poster Session 2
11:15	Applications	REMOT: A Hardware-Software Architecture for Attention-Guided Multi-Object Tracking with Dynamic Vision Sensors on FPGAs	Yizhao Gao (University of Hong Kong), Song Wang (University of Hong Kong), and Hayden Kwok-Hay So (University of Hong Kong)
		Accelerating Constraint-Based Causal Discovery by Shifting Speed Bottleneck	Ce Guo (Imperial College London) and Wayne Luk (Imperial College London)
		Co-Design for Energy Efficient and Fast Genomic Search: Interleaved Bloom Filter on FPGA	Marius Knaust (Zuse Institute Berlin), Enrico Seiler (Freie Universität Berlin), Knut Reinert (Freie Universität Berlin), and Thomas Steinke (Zuse Institute Berlin)
		Accelerating SSSP for Power-Law Graphs	Yuze Chi (UCLA), Licheng Guo (UCLA), and Jason Cong (UCLA)
12:15	Best Paper Award and Closing Session		Michael Adler, Paolo Ienne

Poster Session 1 (February 28)

Title	Authors
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA	Mingqiang Huang (Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences), Yucen Liu (Southern University of Science and Technology), Quan Cheng (Southern University of Science and Technology), Shuxin Yang (Southern University of Science and Technology), Kai Li (Southern University of Science and Technology), Junyi Luo (Southern University of Science and Technology), Zhengke Yang (Southern University of Science and Technology), Qiufeng Li (Southern University of Science and Technology), and Hao Yu (Southern University of Science and Technology)
Automated Accelerator Optimization Aided by Graph Neural Networks	Atefeh Sohrabizadeh (UCLA), Yunsheng Bai (UCLA), Yizhou Sun (UCLA), and Jason Cong (UCLA)
Efficient FPGA-based ECDSA Verification Engine For Permissioned Blockchains	Rashmi Agrawal (Boston University), Ji Yang (Xilinx), and Haris Javaid (Xilinx)
End-to-End Acceleration of Homomorphic Encrypted CNN Inference on FPGAs	Tian Ye (University of Southern California), Rajgopal Kannan (US Army Research Lab), and Viktor K. Prasanna (University of Southern California)
FPGA Accelerators for Robust Visual SLAM on Humanoid Robots	Maria Rafaela Gkeka (University of Thessaly), Alexandros Patras (University of Thessaly), Nikolaos Tavoularis (FORTH), Stylianos Piperakis (FORTH), Emmanouil Hourdakis (FORTH), Panos Trahanias (FORTH), Christos D. Antonopoulos (University of Thessaly), Spyros Lalis (University of Thessaly), and Nikolaos Bellas (University of Thessaly)
Hardware Acceleration of Nonparametric Belief Propagation for Efficient Robot Manipulation	Yanqi Liu (Brown University), Theo Guerin (Brown University), Anthony Opipari (University of Michigan), and Ruth Iris Bahar (Brown University)
HMT: A Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for High-Performance Authentication	Rakin Muhammad Shadab (University of Central Florida), Yu Zou (University of Central Florida), Sanjay Gandham (University of Central Florida), Amro Awad (North Carolina State University), and Mingjie Lin (University of Central Florida)
MathRAMs: Configurable Fused Compute-Memory Blocks for FPGAs	Aman Arora (The University of Texas at Austin), Aatman Borda (The University of Texas at Austin), Anand Tanmay (The University of Texas at Austin), Bagus Hanindhito (The University of Texas at Austin), and Lizy John (The University of Texas at Austin)
Synthesized Garbage Collection for FPGA Accelerators	Martha Barker (Columbia University), Martha Kim (Columbia University), and Stephen A. Edwards (Columbia University)

Poster Session 2 (March 1)

Title	Authors
DecGNN: A Framework for Mapping Decoupled GNN Models onto CPU-FPGA Heterogeneous Platform	Bingyi Zhang (University of Southern California), Hanqing Zeng (University of Southern California), and Viktor K. Prasanna (University of Southern California)
FPGA-based Trainable Autoencoder for Communication Systems	Jonas Ney (TU Kaiserslautern), Sebastian Dörner (University of Stuttgart), Matthias Herrmann (TU Kaiserslautern), Mohammad Hassani Sadi (TU Kaiserslautern), Jannis Clausius (University of Stuttgart), Stephan ten Brink (University of Stuttgart), and Norbert Wehn (TU Kaiserslautern)
Highly Scalable Runtime Countermeasure Against Microprobing Attacks on Die-to-Die Interconnections in System-in-Package	Zhenyu Xu (The University of Rhode Island), Thomas Mauldin (The University of Rhode Island), Qing Yang (The University of Rhode Island), and Tao Wei (The University of Rhode Island)
HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers	Yuanlong Xiao (University of Pennsylvania) and Andre DeHon (University of Pennsylvania)
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA	Mohammad Bagherbeik (University of Toronto), Wentao Xu (University of Toronto), Seyed Farzad Mousavi (University of Toronto), Kouichi Kanda (Fujitsu Limited), Hirotaka Tamura (DXR Laboratory), and Ali Sheikholeslami (University of Toronto)
An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGA	Yukui Luo (Northeastern University), Yuheng Zhang (Northeastern University), Shijin Duan (Northeastern University), and Xiaolin Xu (Northeastern University)
SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation	Atefeh Sohrabizadeh (UCLA), Yuze Chi (UCLA), and Jason Cong (UCLA)
Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform	Jiafeng Xie (Villanova University), Pengzhou He (Villanova University), and Tianyou Bao (Villanova University)
Yosys+Odin-II: The Odin-II Partial Mapper with Yosys Coarse-grained Netlists in VTR	Seyed Alireza Damghani (University of New Brunswick) and Kenneth B. Kent (University of New Brunswick)