Technical Program

All times shown in Pacific Standard Time (UTC-8).

All paper sessions are in Cypress Ballroom, and all poster sessions are in Monterey Bay.

Sunday, March 3, 2024

Workshops and Tutorials are listed separately. All workshops and tutorials are included in the conference fee, but may require separate registration in order to manage capacity. Check each event for additional registration requirements.


Monday, March 4, 2024

indicates best paper candidate

09:00 AM-09:10 AM Opening
09:10 AM-10:00 AM Keynote: Security, Synapses, Sustainability, and Superconducting: A Look at Possible Futures for the FPGA
Timothy Sherwood (UC Santa Barbara)
10:00 AM-10:15 AM Break
10:15 AM-11:30 AM Paper Session 1: FPGA Circuit Design
Chair: Raymond Nijssen (Achronix)
CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond.
Alireza Khataei, Kia Bazargan (University of Minnesota)
Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet
Greg Stitt, Wesley Piard, Christopher Crary (University of Florida)
MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs
Shaoxian Xu, Sitong Lu, Zhiyuan Shao, Xiaofei Liao, Hai Jin (Huazhong University of Science and Technology)
Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine (Short Paper)
Andy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao (Jane Street)
11:30 AM-12:30 PM Poster Session 1
12:30 PM-01:45 PM Lunch
Location: Plaza
01:45 PM-03:00 PM Paper Session 2: Applications 1
Chair: Aman Arora (Arizona State University)
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits
Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne (EPFL)
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
Jinming Zhuang (University of Pittsburgh), Zhuoping Yang (University of Pittsburgh), Shixin Ji (University of Pittsburgh), Heng Huang (University of Maryland), Alex K. Jones (University of Pittsburgh), Jingtong Hu (University of Pittsburgh), Yiyu Shi (University of Notre Dame), Peipei Zhou (University of Pittsburgh)
LevelST: Stream-based Accelerator for Sparse Triangular Solver
Zifan He (University of California, Los Angeles), Linghao Song (University of California, Los Angeles), Robert F. Lucas (Ansys, Inc.), Jason Cong (University of California, Los Angeles)
A 475 MHz Manycore FPGA Accelerator for RTL Simulation (Short Paper)
Sahand Kashani (EPFL), Mahyar Emami (EPFL), Keisuke Kamahori (University of Washington), Sepehr Pourghannad (ETH), Ritik Raj (Georgia Tech), James R. Larus (EPFL)
03:00 PM-03:15 PM Break
03:15 PM-04:20 PM Paper Session 3: CAD for FPGAs
Chair: Sinan Kaptanoglu (Microchip Corp)
From Topology to Realization in FPGA/VPR Routing
Mahdi Abbaszadeh, Dana L. How (Rapid Silicon)
Formal Verification of Source-to-Source Transformations for HLS
Louis-Noël Pouchet (Colorado State University), Emily Tucker (Colorado State University), Niansong Zhang (Cornell University), Hongzheng Chen (Cornell University), Debjit Pal (University of Illinois at Chicago), Gabriel Rodríguez (CITIC, Universidade da Coruña), Zhiru Zhang (Cornell University)
REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs
Dongjoon Park, Andre DeHon (University of Pennsylvania)
04:20 PM-04:35 PM Break
04:35 PM-05:20 PM Paper Session 4: Datacenter & Cloud
Chair: Paul Chow (University of Toronto)
An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits
Zhenyu Xu (The University of Rhode Island), Miaoxiang Yu (The University of Rhode Island), Jillian Cai (The University of Rhode Island), Saddam Gafsi (Clemson University), Judson Douglas Ryckman (Clemson University), Qing Yang (The University of Rhode Island), Tao Wei (The University of Rhode Island)
SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC
Will Lin (University of California, San Diego), Yizhou Shan (University of California, San Diego), Ryan Kosta (University of California, San Diego), Arvind Krishnamurthy (University of Washington), Yiying Zhang (University of California, San Diego)
05:20 PM-06:30 PM Adjourn & Steering Committee Meeting
06:30 PM-09:00 PM Banquet
Invited Panel on "Do FPGAs Still Have a Place in the Era of AI?"
FPGA Routing Contest: Introduction and winner announcements
Location: Cypress Ballroom


Tuesday, March 5, 2024

indicates best paper candidate

09:00 AM-09:10 AM Chair's Announcement
09:10 AM-10:00 AM Keynote: My Fifteen Year Journey of Deploying FPGA Accelerated Solutions
Prabhat K. (PK) Gupta (Innovex, LLC)
10:00 AM-10:15 AM Break
10:15 AM-11:30 AM Paper Session 5: Applications 2
Chair: Peipei Zhou (University of Pittsburgh)
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network
Chunyou Su (The Hong Kong University of Science and Technology), Linfeng Du (The Hong Kong University of Science and Technology), Tingyuan Liang (The Hong Kong University of Science and Technology), Zhe Lin (Sun Yat-sen University), Maolin Wang (ACCESS), Sharad Sinha (Indian Institute of Technology Goa), Wei Zhang (The Hong Kong University of Science and Technology)
HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs
Manoj Bheemasandra Rajashekar, Xingyu Tian, Zhenman Fang (Simon Fraser University)
A Statically and Dynamically Scalable Soft GPGPU
Martin Langhammer, George A. Constantinides (Imperial College London)
Evaluating Versal AI engines for option price discovery in market risk analysis (Short Paper)
Mark Klaisoongnoen (University of Edinburgh), Nick Brown (University of Edinburgh), Tim Dykes (Hewlett Packard Enterprise), Jessica R. Jones (Hewlett Packard Enterprise), Utz-Uwe Haus (Hewlett Packard Enterprise)
11:30 AM-12:30 PM Poster Session 2
12:30 PM-01:45 PM Lunch
Location: Plaza
01:45 PM-02:50 PM Paper Session 6: High-Level Abstractions and Tools for FPGAs
Chair: Sitao Huang (University of California, Irvine)
Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing
Jiahui Xu, Lana Josipović (ETH Zurich)
POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations
Xiaochen Hao (Peking University), Hongbo Rong (Parallel Computing Lab, Intel), Mingzhe Zhang (Tsinghua University), Ce Sun (University of Science and Technology of China), Hong Jiang (Intel), Yun Liang (Peking University & Beijing Advanced Innovation Center for Integrated Circuits)
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang (Peking University)
02:50 PM-03:05 PM Break
03:05 PM-04:10 PM Paper Session 7: Machine Learning
Chair: George A. Constantinides (Imperial College London)
FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs
Shulin Zeng (Tsinghua University, Infinigence-AI), Jun Liu (Shanghai Jiao Tong University, Infinigence-AI), Guohao Dai (Shanghai Jiao Tong University, Infinigence-AI), Xinhao Yang (Tsinghua University, Infinigence-AI), Tianyu Fu (Tsinghua University, Infinigence-AI), Hongyi Wang (Tsinghua University, Infinigence-AI), Wenheng Ma (Tsinghua University), Hanbo Sun (Tsinghua University), Shiyao Li (Tsinghua University, Infinigence-AI), Zixiao Huang (Tsinghua University), Yadong Dai (Infinigence-AI), Jintao Li (Infinigence-AI), Zehao Wang (Infinigence-AI), Ruoyu Zhang (Infinigence-AI), Kairui Wen (Infinigence-AI), Xuefei Ning (Tsinghua University), Yu Wang (Tsinghua University)
Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic
Daniel Gerlinghoff (Institute of High Performance Computing (IHPC), Agency for Science, Technology and Research (A*STAR)), Benjamin Chen Ming Choong (Institute of High Performance Computing (IHPC), Agency for Science, Technology and Research (A*STAR)), Rick Siow Mong Goh (Institute of High Performance Computing (IHPC), Agency for Science, Technology and Research (A*STAR)), Weng-Fai Wong (National University of Singapore), Tao Luo (Institute of High Performance Computing (IHPC), Agency for Science, Technology and Research (A*STAR))
A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA
Yizhao Gao, Baoheng Zhang, Yuhao Ding, Hayden Kwok-Hay So (University of Hong Kong)
04:10 PM-04:30 PM Best Paper Award and Closing Remarks
Location: Cypress Ballroom


Poster Session 1 (March 4)

11:30am – 12:30pm

Title Authors
DynaRapid: From C to FPGA in a Few Seconds Andrea Guerrieri (EPFL & HES-SO Valais-Wallis), Srijeet Guha (EPFL), Lana Josipovic (ETH Zurich), Paolo Ienne (EPFL)
Design and Implementation of a Primary Visual Cortex Pathway Model Based on Opponent-process Theory Hui Wei, Jingyong Ye, Yutong Chen, Heng Wu (Laboratory of Algorithms for Cognitive Models, School of Computer Science, Fudan University)
Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient and Robust Design Andy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao (Jane Street)
XUNI: Virtual Machine Abstraction for Self-contained and Multi-tenant Cloud FPGAs Zelin Wang (Institute of Computing Technology, Chinese Academy of Sciences & University of Chinese Academy of Sciences), Guiyuan Zhu (ShanghaiTech University & Institute of Computing Technology, Chinese Academy of Sciences), Yunhai Liu (Institute of Computing Technology, Chinese Academy of Sciences & University of Chinese Academy of Sciences), Yisong Chang (Institute of Computing Technology, Chinese Academy of Sciences & University of Chinese Academy of Sciences), Ke Zhang (Institute of Computing Technology, Chinese Academy of Sciences & University of Chinese Academy of Sciences), Mingyu Chen (Institute of Computing Technology, Chinese Academy of Sciences & University of Chinese Academy of Sciences)
ISO-TENANT: Rethinking FPGA Power Distribution Network (PDN): A Hardware Based Solution for Remote Power Side Channel Attacks in FPGA. Muhammed Kawser Ahmed, Christophe Bobda (University of Florida)
Accelerating Autonomous Path Planning on FPGAs with Sparsity-Aware HW/SW Co-Optimizations Xiaoyu Niu (Beijing Institute of Technology), Yanjun Zhang (Beijing Institute of Technology), Yifan Zhang (University of California, Irvine), Hongzheng Tian (University of California, Irvine), Bo Yu (Shenzhen Institute of Artificial Intelligence and Robotics for Society), Shaoshan Liu (Shenzhen Institute of Artificial Intelligence and Robotics for Society), Sitao Huang (University of California, Irvine)
Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels Hassan Nassar, Philipp Machauer, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jörg Henkel (Karlsruhe Institute of Technology (KIT))
FPGA-Placement via Quantum Annealing Thore Gerlach (Fraunhofer IAIS), Stefan Knipp (Thales Deutschland GmbH), David Biesner (Fraunhofer IAIS), Stelios Emmanouilidis (Fraunhofer IAIS), Klaus Hauber (Thales Deutschland GmbH), Nico Piatkowski (Fraunhofer IAIS)
Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine (short) Andy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao (Jane Street)
A 475 MHz Manycore FPGA Accelerator for RTL Simulation (short) Sahand Kashani (EPFL), Mahyar Emami (EPFL), Keisuke Kamahori (University of Washington), Sepehr Pourghannad (ETH), Ritik Raj (Georgia Tech), James R. Larus (EPFL)


Poster Session 2 (March 5)

11:30am – 12:30pm

Title Authors
A Flexible, Fast, Low Bandwidth Block-based Acceleration Architecture for CNN Inference on FPGAs Yan Chen, Kiyofumi Tanaka (Japan Advanced Institute of Science and Technology)
E4SA: An Ultra-Efficient Systolic Array Architecture for 4-Bit Convolutional Neural Networks Geng Yang, Jie Lei, Zhenman Fang, Jiaqing Zhang, Junrong Zhang, Weiying Xie, Yunsong Li (Xidian University)
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach Stéphane Pouget (University of California, Los Angeles), Louis-Noël Pouchet (Colorado State University), Jason Cong (University of California, Los Angeles)
Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function Yiyue Jiang (Northeastern University), Andrius Vaicaitis (Maynooth University), John Dooley (Maynooth University), Miriam Leeser (Northeastern University)
AutoHammer: Breaking the Compilation Wall Between Deep Neural Network and Overlay-based FPGA Accelerator Kai Qian (Fudan University), Zheng Liu (Fudan University), Yinqiu Liu (Nanyang Technological University), Haodong Lu (Fudan University), Zexu Zhang (Fudan University), Ruiqiu Chen (Fudan University), Kun Wang (Fudan University)
A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs Hongzheng Chen (Cornell University), Jiahao Zhang (Tsinghua University), Yixiao Du (Cornell University), Shaojie Xiang (Cornell University), Zichao Yue (Cornell University), Niansong Zhang (Cornell University), Yaohui Cai (Cornell University), Zhiru Zhang (Cornell University)
HR-GCN: An Efficient GCN Accelerator for Heterogeneous Graph Data and R-GCN Model Shengjun Xu, Wenlu Peng, Wenjin Huang, Qi Liu, Yihua Huang (Sun Yat-sen University)
Hermes: Enhancing Extensibility in High-Level Synthesis through Multi-Level IRs Ruifan Xu, Jin Luo, Yun Liang (Peking Univerisity)
Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks Qizhe Wu, Letian Zhao, Yuchen Gui, Huawen Liang, Xiaotian Wang, Xi Jin (University of Science and Technology of China)
Cross-FPGA Power Estimation from High Level Synthesis via Transfer-Learning Zhigang Wei (The University of Austin at Texas), Aman Arora (Arizona State University), Emily Shriver (Intel Labs), Lizy John (The University of Austin at Texas)
Evaluating Versal AI engines for option price discovery in market risk analysis (short) Mark Klaisoongnoen (University of Edinburgh), Nick Brown (University of Edinburgh), Tim Dykes (Hewlett Packard Enterprise), Jessica R. Jones (Hewlett Packard Enterprise), Utz-Uwe Haus (Hewlett Packard Enterprise)