ID Title
4 Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits
10 HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs
21 A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA
28 Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet
31 REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs
38 Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
57 FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs
61 Formal Verification of Source-to-Source Transformations for HLS
64 SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC
65 An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits
67 POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations
68 A Statically and Dynamically Scalable Soft GPGPU
88 LevelST: Stream-based Accelerator for Sparse Triangular Solver
111 SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff Design Space Exploration
139 Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing
141 MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs
158 From Topology to Geometry & Realization in FPGA/VPR Routing
172 GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network
182 Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine
191 Evaluating Versal AI engines for option price discovery in market risk analysis
262 A 475 MHz Manycore FPGA Accelerator for RTL Simulation
268 CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond
359 Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic