Keynote: FPGAs and their evolving role in Domain Specific Architectures: a case study of the AMD 400G Adaptive SmartNIC/DPU SoC

Jaideep Dastidar

Senior Fellow
SoC Architect of Domain Specific Accelerators

Abstract: Domain Specific Architectures (DSA) typically apply heterogeneous compute elements such as FPGAs, GPUs, AI Engines, TPUs, etc. towards solving domain-specific problems, and have their accompanying Domain Specific Software. FPGAs have played a prominent role in DSAs for AI, Video Transcoding, Network Acceleration etc. This talk will start by going over a brief historical survey of FPGAs in DSAs and an emerging trend in Domain Specific Accelerators, where the programmable logic element is paired with other heterogeneous compute or acceleration elements. The talk will then perform a case study of AMD’s 400G Adaptive SmartNIC/DPU SoC and the considerations that went into that DSA. The case study includes where, why, and how the programmable logic element was paired with other hardened offload accelerators and embedded processors with the goal of striking the right balance between Software Processing on the embedded cores, Fastpath ASIC-like processing on the Hardened Accelerators, and Adaptive and Composable processing on the integrated FPGA. The talk will describe the data movement between various network, storage and interface acceleration elements and their shared and private memory resources. Throughout the talk, we will focus on the tradeoffs between the FPGA element and the rest of the heterogeneous compute or acceleration elements as they apply to SmartNIC/DPU offload acceleration.

Speaker: Jaideep Dastidar is a Senior Fellow at AMD, and SoC Architect of Domain Specific Accelerators and Adaptive SoCs across the Datacenter, Communications, and Automotive/Industrial space. Jaideep is also the Lead Architect of AMD’s 400G Adaptive SmartNIC/DPU SoC described in this keynote address. He came to AMD as a Distinguished Engineer, by way of Xilinx. Prior to AMD-Xilinx, Jaideep was a Distinguished Engineer in Freescale’s Networking Systems & Architecture Group, and Master Technologist at Hewlett-Packard Enterprise, doing ProLiant Server Architecture & Design. Jaideep has a B.S. in Electrical Engineering from the University of Texas at Austin, and an MSEE from the Oregon Graduate Institute. He has co-authored IEEE and ACM publications and has over 50 pending and granted patents.